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Presettable synchronous BCD decade counter IC - 74HC160
Presettable synchronous BCD decade counter IC - 74HC160
Presettable synchronous BCD decade counter IC - 74HC160
Presettable synchronous BCD decade counter IC - 74HC160
Presettable synchronous BCD decade counter IC - 74HC160
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Presettable synchronous BCD decade counter IC - 74HC160 The 74HC Series 74HC160 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) …
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Presettable synchronous BCD decade counter IC - 74HC160 The 74HC Series 74HC160 is a high-speed Si-gate CMOS device and is pin-compatible with low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET, and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies the serial cascading of the counters. Both counts enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.  Pinout: Pinout Of 74HC160 IC Symbol  Pin  Description MR   1 Asynchronous master reset (active LOW) CP   2 Clock input (LOW-to-HIGH, edge triggered) D0, D1, D2, D3   3, 4, 5, 6 Data input CEP 7 Count enable input GND   8 Ground (0 V) PE  9 Parallel enable input (active LOW) CET  10 Count enable carry input Q0, Q1, Q2, Q3  14, 13, 12, 11 Flip-flop output TC  15 Terminal count output VCC   16 Supply Voltage Applications: Television sets Home-sound sets Multimedia systems All mains-fed audio systems Car Audio (boosters). Package Includes: Selected qty of IC - 74HC160 Specifications: Series  74HC Function Presettable Counter Product Type Counter Shift Registers Counter Type Presettable Number of Circuits 1 Propagation Delay Time 37 ns Supply Voltage 2V - 6V Operating Temperature -55°C - +125°C Mounting Type Through Hole

  • Synchronous counting and loading
  • Two count enable inputs for n-bit cascading
  • Positive-edge triggered clock
  • Asynchronous reset
  • Output capability: standard
  • ICC category: MSI
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